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Design & Consulting GesmbH
MC8051 IP Core
Synthesizeable VHDL Microcontroller IP-Core
User Guide
Web: http://oregano.at/services/8051.htm Contact: MC8051@oregano.at
Version 1.1 June 2002
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8051 IP Core - Overview
Key Features
Fully synchronous design Instruction set compatible to the industry standard 8051 microcontroller Optimized architecture enables fast one to four clocks per OP code Up to 10 times faster due to completely new architecture User selectable number of timers/counters as well as serial interface units Active timer/counter and serial interface units selectable via additional special function register Optional implementation of the multiply command (MUL) using a parallel multiplier unit Optional implementation of the divide command (DIV) using a parallel divider unit Optional implementation of the decimal adjustment command (DA) No multiplexed I/O ports 256 bytes internal RAM Up to 64 Kbytes ROM and up to 64 Kbytes RAM Source code available free of charge under the GNU LGPL license Technology independent, clear structured, well commented VHDL source code Easily expandable by adapting/changing VHDL source code Parameterizeable via VHDL constants
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8051 IP Core - Block Diagram
The starting from the top level module and its submodules are depicted in figure 1. The toplevel signal names are shown as well as the three memory blocks used in the design. The user selectable number of serial interfaces and timer/counter units is indicated by the dotted line between the modules MC8051_siu and MC8051_tmrctr.
clk reset all_t0_i all_t1_i all_rxd_i int0_i int1_i p0_i p1_i p2_i p3_i
N
N N
MC8051_siu
MC8051_siu
N N N
all_rxdwr_o all_txd_o all_rxd_o
N
N
MC8051_alu
N N
MC8051_tmrctr
MC8051_tmrctr
8 8 8 8
8 8 8 8
p0_o p1_o p2_o p3_o
MC8051_control
MC8051_core
MC8051_top
MC8051_ram (128x8 bit)
MC8051_rom (up to 64kx8 bit)
MC8051_ramx (up to 64kx8 bit)
figure 1: Block diagram of the 8051 microcontroller IP-core.
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Signal Name clk reset all_t0_i all_t1_i all_rxd_i int0_i int1_i p0_i p1_i p2_i p3_i all_rxdwr_o all_txd_o all_rxd_o p0_o p1_o p2_o p3_o
Description System clock. Only rising edge used. Asynchronous reset of all flip-flops. Timer/counter 0 inputs. Timer/counter 1 inputs. Receive data input for serial interface units. Interrupt 0 inputs. Interrupt 1 inputs. Parallel port 0 input. Parallel port 1 input. Parallel port 2 input. Parallel port 3 input. Data direction signal for bidirectional rxd input/output (high = output) data. Transmit data output for serial interface unit. Data output for mode 0 operation of serial interface unit. Parallel port 0 output. Parallel port 1 output. Parallel port 2 output. Parallel port 3 output.
table 1: Top level signal name.
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Design Hierarchy
The design hierarchy and the corresponding VHDL files are depicted in figure 2.
testbench tb_MC8051_top_ tb_MC8051_top_sim
external RAM model MC8051_ramx_ MC8051_ramx_rtl
internal RAM model MC8051_ram_ MC8051_ram_rtl
microcontroller core MC8051_core_ MC8051_core_struc
ROM model MC8051_rom_ MC8051_rom_rtl
timer/counter MC8051_tmrctr_ MC8051_tmrctr_rtl
ALU MC8051_alu_ MC8051_alu_struc
serial interface MC8051_siu_ MC8051_siu_rtl
control unit MC8051_control_ MC8051_control_struc
alumux_ alumux_rtl
alucore_ alucore_rtl
addsub_core_ addsub_core_ struc
comb_mltplr_ comb_mltplr_rtl
comb_divider_ comb_divider_rtl
dcml_adjust_ dcml_adjust_rtl
memory unit control_mem_ control_mem_rtl
FSM control_fsm_ control_fsm_rtl
addsub_cy_ addsub_cy_rtl
addsub_ovcy_ addsub_ovcy_rtl
figure 2: Design hierarchy of the 8051 microcontroller IP-core.
The VHDL source files have been consistently named throughout the whole design: * * * * VHDL entities VHDL architectures VHDL configurations entity-name_.vhd entity-name_rtl.vhd for modules containing logic entity-name_struc.vhd for modules just connecting submodules entity-name_rtl_cfg.vhd entity-name_struc_cfg.vhd
The core itself is made up of the submodules timer/counter, ALU, serial interface, and control unit. RAM or ROM blocks are most often generated corresponding to the selected target technology and are therefore instantiated in the highest design hierarchy. Generated RAM blocks and BIST structures - for ASIC production test integration - can be easily added at this level of the design.
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Clock Domains
The 8051 IP core is a fully synchronous design. There is a single clock signal that controls the clock input of every storage element. Clock gating is not used. The clock signal is not fed into any combinatorial element. The interrupt input lines are synchronized to the global clock signal using a standard two-level synchronization stage because they may be driven by external circuitry that operates with another clock. The parallel port input signals are not synchronized that way. If the user decides that there is also the need for synchronizing these signals it may be added easily.
Memory Interfaces
Due to the optimized architecture the signals coming from and going to the memory blocks have not been registered. So during synthesis input and output timing constraints should be placed on the corresponding ports and synchronous memory blocks should be used for the MC8051 IP-core.
Configuring the 8051 IP Core
In the following the parameterizability of the 8051 microcontroller IP-core design will be discussed and information for embedding the IP-core in larger designs will be given.
Timer/Counter, Serial Interface, and Interrupts
The original microcontroller design offered only 2 timer/counter units, one serial interface, and two external interrupt sources. 8051 derivates later offered more of these resources on chip. Since this is sometimes a limiting factor we decided to implement some sort of parameterization in the 8051 IP core. This 8051 microcontroller IP-core offers the capability to generate up to 256 of these units by simply changing a VHDL constant's value. In the VHDL source file MC8051_p.vhd the constant C_IMPL_N_TMR can take values from 1 to 256 to control this feature. Values out of this interval result in a non functioning configuration of the core. Figure 3 shows the corresponding lines of VHDL code.
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------------------------------------------------------------------------------ Select how many timer/counter units should be implemented -- Default: 1 constant C_IMPL_N_TMR : integer := 1; ---------------------------------------------------------------------------------------------------------------------------------------------------------- Select how many serial interface units should be implemented -- Default: C_IMPL_N_TMR ---(DO NOT CHANGE!)--constant C_IMPL_N_SIU : integer := C_IMPL_N_TMR; ---------------------------------------------------------------------------------------------------------------------------------------------------------- Select how many external interrupt-inputs should be implemented -- Default: C_IMPL_N_TMR ---(DO NOT CHANGE!)--constant C_IMPL_N_EXT : integer := C_IMPL_N_TMR; -----------------------------------------------------------------------------
figure 3: VHDL source code for configuring the number of timer/counter units, serial interfaces, and external interrupts.
At the moment the three constants C_IMPL_N_TMR, C_IMPL_N_SIU, C_IMPL_N_EXT cannot be changed independently. Incrementing constant C_IMPL_N_TMR by one means to generate two additional timer/counter units, one additional serial interface, and two additional external interrupt sources. To be able to reach all registers of the generated units without changing the address space of the microcontroller only two 8bit registers are inferred as additional special function registers. These are TSEL (address 0x8Eh for timer/counter units) and SSEL (address 0x9Ah for serial interface units). If these registers point to a not existent device number, the default unit number 1 is selected. The circuit is depicted in figure 4.
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TCON1
EN CLK
1D
TCON data input
TCON2
EN CLK
1D
MUX
256x8 bit to 1x8 bit
TCONN data output
TCON256
EN CLK
1D
TSEL
EN CLK
1D
selection of the Nth unit through additional special function register TSEL
DECODER 8 to 256
figure 4: Selection of a TCON register using additional TSEL register.
If an interrupt occurred during this very device was not selected by e.g. TSEL, the corresponding interrupt flag stays set until the matching interrupt service routine is executed. Subsequent interrupts during the time the device has not been selected thou result in only one single call to the interrupt service routine.
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Optional Instructions
In some cases it makes sense to not implement instructions which are not needed and consume furthermore much chip area. Such instructions are 8bit multiplication, 8bit division, and 8bit decimal correction. Therefore the MUL instruction for 8bit multiplication can be skipped when the VHDL constant C_IMPL_MUL in the MC8051_p.vhd source file is set to 0. Equally the 8bit division DIV can be skipped through setting the VHDL constant C_IMPL_DIV to 0 and the decimal correction instruction can be skipped by setting the constant C_IMPL_DA to 0. The corresponding lines of VHDL source code can be seen in figure 5.
------------------------------------------------------------------------------ Select whether to implement (1) or skip (0) the multiplier -- Default: 1 constant C_IMPL_MUL : integer := 1; ---------------------------------------------------------------------------------------------------------------------------------------------------------- Select whether to implement (1) or skip (0) the divider -- Default: 1 constant C_IMPL_DIV : integer := 1; ---------------------------------------------------------------------------------------------------------------------------------------------------------- Select whether to implement (1) or skip (0) the decimal adjustment command -- Default: 1 constant C_IMPL_DA : integer := 1; -----------------------------------------------------------------------------
figure 5: Code fragment showing how instructions can be skipped.
The gain in terms of chip area when not implementing all three optional instructions is approximately 10 %.
Parallel I/O Ports
The MC8051 IP-core offers just as the original 8051 microcontroller 4 bidirectional 8bit I/O ports to conveniently exchange data with the microcontroller's environment. To ease integration of our core for IC design the original's multi-function ports have not been rebuilt and all signals (e.g. serial interface, interrupts, counter inputs, and interface to external memory) have been fed separately out of the core (see figure 1). The basic structure of the parallel I/O ports is shown in figure 6.
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Q
to MC8051_core input port px_i<7:0>, where it is directly fed into a register input (dashed registers mark synchronisation registers if data is not in sync with the system clock)
D
Q
D
internal (e.g. some FPGAs) or external pull up resistor
Pad
from port px_o<7:0> of MC8051_core, where it comes directly form a register.
figure 6: Basic structure of the parallel I/O ports.
Verification
Verification of the core was accomplished by simulating the VHDL code and comparing the results of the executed program (i.e. ROM contents) with the results produced by an industry standard 8051 simulator (http://www.keil.com/demo/evaldl.asp?p=C51). After simulation the contents of a certain memory area is written to a file both for the standard 8051 simulator (using the command save keil.hex 0x00,0xFF) and the VHDL code simulation (e.g. using the script write2file.do, producing the file regs.log in the simulation directory). The resulting text files have to be identical. To be able to feed the compiled assembler file from the Keil development software to the VHDL code simulation a short C program is provided in the latest distribution of the IP core. It converts the Intel hex format file into a text file containing binary 8 bit data, suited for being read by the VHDL simulator (file MC8051_rom.dua in the simulation directory).
Deliverables
Extract the MC8051.zip file as is using the directory tree we recommend. There are already scripts for synthesis using Synopsys's DesignCompiler for ASIC design and Synplicity's Synplify for FPGA design. Additionally there are scripts for RTL simulation using Mentor's/Modeltech's Modelsim. See figure 7 for an overview of the MC8051 directory tree.
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MC8051
dc docu msim synpl tb vhdl vss
db lib log reports scr
figure 7: Directory tree in which the MC8051 IP-core is distributed.
Directory dc dc/db dc/lib dc/log dc/reports dc/scr docu msim synpl tb vhdl vss
Contents Synthesis with Design Compiler DC databases DC compiled HDL files DC synthesis log files DC synthesis report files DC synthesis script files Documentation Modelsim simulation directory Synthesis with Synplicity's Synplify Testbench and memory models Synthesizeable, well commented VHDL source code Simulation with Synopsys VSS
table 2: Directory tree: Brief description.
Document Revisions
Version 1.0, January 2002: Initial version of the MC8051 IP Core User Guide. Version 1.1, June 2002: Added document history and added some details to the verification paragraph. Removed scr directory from project tree.
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